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TRAMS - European researchers develop techniques to design more robust memory chips

Universitat Politècnica De Catalunya (UPC) : 03 January, 2013  (Special Report)
European funded project investigates advanced countermeasure techniques to compensate the dramatic variability device phenomena on Embedded Memories for future technologies.
TRAMS - European researchers develop techniques to design more robust memory chips

The Seventh Framework Program for Research and Technological Development funded European project TRAMS (Tera-scale Reliable Adaptive Memory Systems) investigates the impact of the statistical variability on tera-scale embedded SRAM and DRAM memories based on sub 16 nm technology generations when using planar bulk, 3D-FinFET, Carbon Nanotubes and III_V/Ge technologies. The Universitat Politècnica de Catalunya BarcelonaTech (UPC) leads the project.

The statistical variability introduced by the discreteness of charge and matter has become a major obstacle to scaling and integration. The impact of this statistical variability on embedded memories is particularly dramatic, by slowing supply voltage scaling, especially for SRAM and DRAM, and threatening the continuation of area scaling that helps drive integration targets for Systems on Chip.

The consortium of the TRAMS project has investigated on the implementation of efficient countermeasure techniques oriented to tolerate these limiting phenomena in order to produce robust circuits that keep the technology progress trend. New adaptive, mechanisms have been investigated and evaluated for different levels of variability.

Run-time adaptability has been granted through novel two level mechanisms. The first level consists of sensors placed within the memory; and the second level reconfigures dynamically the memories based on the sensor data in order to meet the performance and power targets.

Original memory variability-aware pro-active adaptable structures have been proposed; our implementation on memory circuits show that we can tolerate variability effects enlarging the life of the memory more that 400%.

Advanced Fault-Tolerating architectures have also been investigated for technologies with very high variability and aging. This last stage of research has shown the counter intuitive principle that it is possible to improve reliability by introducing forced noise in the input lines of the architecture (Degradation Stochastic Resonance effect). 

Technology Backgrounder

Technology projections indicate that future electronic devices will keep shrinking, being faster and consuming less energy per operation. In the next decade, a single chip will be able to perform trillions of operations per second and provide trillions of bytes per second in off-chip bandwidth. This is the so-called Terascale Computing era, where terascale performance will be mainstream, available in personal computer, and being the building block of large data centers with petascale computing capabilities. However, these smaller devices will be much more susceptible to faults and its performance will exhibit a significant degree of variability. As a consequence, to unleash these impressive computing capabilities, a major hurdle in terms of reliability has to be overcome. The TRAMS project is the bridge for reliable, energy efficient and cost effective computing in the era of nanoscale challenges and teraflop opportunities.

The International Roadmap for Semiconductors (ITRS) report indicates that the Metal Oxide Semiconductor devices (MOS or MOS like devices) will be ultimately scaled down below 10 nm in several years. The CMOS technologies after the 16 nm technology generation are called Late CMOS technologies and will include novel multigate device architectures and novel channel and gate stack materials. Reliability issues are expected to be exacerbated to in sub-10 nm CMOS technology.

Beyond-CMOS emerging technologies will reach device dimensions reduction below 5 nm utilising among others, nanowire transistors, quantum devices, carbon nanotubes, graphene, or molecular electronics. Both the Late CMOS and the Beyond CMOS technologies hold the promise of a significant increase in device integration density complemented by an increase in system performance and functionality. However, a dramatic reduction in single device quality is also expected, complemented by increase in statistical variability, severe reduction of the signal to noise ratio, and severe reliability problems. Therefore, alternative device solutions and computation paradigms need to be investigated to keep the technology evolution pace in such a challenging scenario.

Memory cells and, in general, system architectures intended for nanotechnologies (both late CMOS and emerging devices) need to address the variability and reliability problem and should be capable of solving or at least largely alleviating it. In order to build reliable nanosystems, the TRAMS project addresses a specific variability and reliability-aware analysis and design flow as well as a hierarchical tolerance design. In such a tera-device multicore system the main idea will be to define countermeasure techniques at circuit and architecture design levels. The objective of this project is to investigate in depth potential new design alternatives and paradigms, which will be able to provide reliable memory systems out of highly unreliable nanodevices at a reasonable cost and design effort.

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